1. Field of the Invention
The present disclosure relates generally to a semiconductor fabrication and, more particularly, to a shallow trench isolation (hereinafter referred to as “STI”) structure and a method for preventing the occurrence of voids in an O3-tetra ethyl ortho silicate (hereinafter referred to as “TEOS”) layer and seams in the upper part of the STI structure.
2. Background of the Related Art
As the technology for a semiconductor device advances, the semiconductor device needs to achieve a high integration and operate at a high speed and, as a result, a high precision in a pattern size is required to form a miniaturized pattern. In detail, not only the width of the area for devices, but also the width of a device isolation structure, which constitute a large portion of a semiconductor device, have to be decreased to guarantee a relatively wider area for the devices. Thus, a pattern to form a device isolation structure as well as a pattern to form other devices has to be miniaturized and have the high precision.
For the device isolation structure of prior arts, a LOCOS process has been widely employed. However, the device isolation achieved by the LOCOS process has several shortcomings such as well-known bird's-beak. The bird's-beak, in particular, is formed at the edges of the device isolation structure and, therefore, increases the area of the device isolation structure and generates a leakage current.
Accordingly, various methods to solve such problems in the conventional LOCOS process have been suggested. One popular method is to form an STI structure as the device isolation.
FIGS. 1 through 5 are cross-sectional views illustrating an STI structure fabrication method in accordance to a prior art.
Referring to FIG. 1, a pad oxide layer 12 having the thickness of 150 Å is deposited on a silicon substrate 11. Subsequently, a pad nitride layer 13 having the thickness of 1600 Å is deposited on the pad oxide layer 12. Through a photolithography process, the pad oxide layer 12 and the pad nitride layer 13 are then patterned to expose a predetermined part of the surface of the silicon substrate 11. The exposed part of the silicon substrate is then etched by a predetermined depth to form a trench 14.
Referring to FIG. 2, a thin thermal oxide layer 15 is then grown on the inside of the trench 14 by a sacrificial oxidation process. The thin thermal oxide layer 15 cures damages caused during the etching process. Subsequently, an O3-TEOS oxide layer 16 is filled into the trench 14 and deposited on the entire surface of the resulting structure.
Referring to FIG. 3, a chemical mechanical polishing (hereinafter referred to as “CMP”) process is performed for the O3-TEOS oxide layer 16 to expose the pad nitride layer 13.
Referring to FIG. 4, the pad nitride layer 13 is removed by a wet etch.
Referring to FIG. 5, the pad oxide layer 12 is removed by dipping the resulting structure into an HF solution for more than 1.5 times of the optimum time for removing an oxide layer. As a result, an STI structure is completed.
However, in accordance with the prior art, seams in the top of the STI structure and voids in the O3-TEOS oxide layer can be generated, thereby detrimentally affecting the characteristic of the semiconductor device such as reliability and completeness.